Synthesis strategies based on the appropriate use of inductance effects

ABSTRACT

A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed. The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires or the width of the ground wires. The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedances at the junction between the branches are substantially equal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Patent Application 60/335,157, filed Nov. 13, 2001, and U.S. Provisional Patent Application 60/374,208, filed Apr. 19, 2002, which are both incorporated herein by reference.

BACKGROUND

Inductance effects on interconnects is an emerging concern in high-performance integrated circuits. Because inductance is related directly to the frequency at which an integrated circuit operates, its effects have traditionally been negligible for circuits operating at relatively low clock speeds. With recent advances in integrated circuit technology, however, higher clock speeds are now attainable at which inductance effects can no longer be ignored.

In general, signal propagation in an integrated circuit can be characterized as operating within two distinct subdomains: the domain where inductance effects are negligible (the rc domain), and the domain where inductance effects are appreciable (the rlc domain). Most wire layouts in an integrated circuit operate in the rc domain where effects from inductance are negligible and where characteristic diffusion times are much longer than the propagation time of electromagnetic waves. Signal propagation on a wire is typically measured in terms of the time needed for the output voltage of a wire to reach one-half of its input value, a value generally accepted as sufficient to produce a transition at a transistor located at the output. This time is referred to as the 50% time delay (t_(50%)). A well-known approximation of the 50% time delay for an open-ended line operating in the rc domain, termed the Sakurai 50% time delay equation, is: t _(50%)=0.377rcL ²+0.693R _(tr) cL  (1) where L is the length of the line, r and c are the resistance and capacitance per unit length of the line, respectively, and R_(tr) is the resistance of the source driving the line. As can be seen from equation (1), the delay exhibits a quadratic increase for longer line lengths L. When delays on rc lines become large, repeaters are often inserted to restore the signal voltage to its maximum driving voltage. Because signal propagation in the rc domain is well-defined and understood, circuit designers and engineers usually attempt to minimize any inductance effects so as not to perturb their traditional design styles. Thus, the natural tendency will be to attempt to minimize inductance so as not to get out of the rlc domain. This approach, however, does not allow signal propagation to occur at its highest possible speed and requires the frequent use of repeaters.

SUMMARY

A synthesis and layout method, such that the time delay is controlled by the wave propagation delay, is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire sandwiched between opposing parallel ground wires. In particular, one of the physical parameters that defines the wiring layout is adjusted to alter the loop inductance, loop resistance, and total capacitance of the wiring layout to create an rlc relationship that maximizes the signal propagation speed on the signal wire and enables transmission-line behavior. In one particular implementation of the method, the physical parameter that is adjusted is the wire separation between the signal wire and the ground wires. In another implementation of the method, the width of the ground wires is the physical parameter that is adjusted.

The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, the first branch is configured to have a rlc relationship that maximizes the signal propagation speed. A branch directly downstream of, and coupled with, the first branch at a junction may be adjusted so that the impedance at the junction matches that of the first branch. The method may include determining whether adjustment of the downstream branch requires a physical parameter of the wiring layout to exceed a maximum possible value. If the maximum possible value of a physical parameter is exceeded, a repeater may be inserted at the beginning of the downstream branch.

The foregoing and additional features and advantages of the invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an overview of an exemplary clock tree having a balanced H-tree design.

FIG. 2 shows a portion of the clock tree of FIG. 1 in greater detail, including a sandwich-style wiring layout.

FIG. 3 is a cross-sectional view schematically showing the physical parameters of an exemplary sandwich-style wiring layout of FIG. 2.

FIG. 4 is a flowchart of a general method of configuring a wiring layout.

FIG. 5 is a circuit diagram showing the electrical characteristics of a branch of a sandwich-balanced H-tree.

FIG. 6 is a cross-sectional view schematically showing the physical parameters used to calculate the inductance of a branch of a sandwich balanced H-tree.

FIG. 7 is a graph comparing the partial self inductance of an exemplary wiring layout as calculated by FastHenry and by the disclosed simplified expression.

FIGS. 8(A) and 8(B) are cross-sectional views schematically showing how to calculate the inductance between wires having different wire widths.

FIG. 9 is a graph comparing the partial mutual inductance of an exemplary wiring layout.

FIG. 10 is a graph comparing the capacitance function c₁ with chosen observation values.

FIG. 11 is a graph comparing the capacitance function c₂ with chosen observation values.

FIG. 12 is a flowchart showing a method of calculating a set of optimal wire separations (s).

FIG. 13 is a flowchart showing the method of FIG. 12 in terms of mathematical functions.

FIG. 14 is a graph showing Z₀ as a function of ground wire width g.

FIG. 15 is an exemplary results table as may be generated using the disclosed method.

FIG. 16 is a flowchart for selecting a wire separation s from a set of optimal wire separations.

FIG. 17 is a graph showing the output of an input signal after correcting the rise time.

FIG. 18 is a flowchart for matching the impedance of a downstream branch in a sandwich balanced H-tree and for properly inserting repeaters.

FIG. 19 is an overview of five branches of a sandwich balanced H-tree clock tree that have been configured according to the method in FIG. 18.

FIG. 20 is a schematic diagram showing a client-server network that may utilize the disclosed method of configuring a wiring layout.

FIG. 21 is a flowchart showing the use of the disclosed method in the client-server network shown in FIG. 20.

DETAILED DESCRIPTION

As a result of recent advances in digital technology, integrated circuits are being developed that operate at ever increasing clock speeds. With the latest generation of microprocessors operating at clock frequencies above 2 GHz, inductance effects caused by high-speed signals propagating on the interconnects of an integrated circuit can no longer be ignored. Instead of analyzing the wiring layouts as conventional rc circuits, the new state-of-the art designs should be analyzed as rlc circuits. Although circuit designers and engineers thrive to minimize the inductance effects of a wiring layout in order to use traditional methods, the inductance effects can be utilized so that the time delay can be made as small as physically possible. As more fully described below, the electric and magnetic properties of a wiring layout having a signal wire in the presence of a ground plane or ground wires may be optimized so as to maximize the signal propagation speed and minimize delays, optimization being used to achieve synthesis.

I. General Considerations

The differential equation that describes a distributed rlc signal wire in the presence of a ground plane is: $\begin{matrix} {{\frac{\partial^{2}{V\left( {x,t} \right)}}{\partial x^{2}} = {{{lc}\frac{\partial^{2}{V\left( {x,t} \right)}}{\partial t^{2}}} + {{rc}\frac{\partial{V\left( {x,t} \right)}}{\partial t}}}},} & (2) \end{matrix}$ where r, l and c are the resistance, inductance and capacitance per unit of length, respectively. Further, V(x, t) is the potential averaged over the transverse coordinates, where x is the longitudinal coordinate and t is the time. A description based on equation (2) presupposes transverse electromagnetic (TEM) propagation (both the electric and the magnetic field transverse to the direction of propagation) and homogeneity of the medium in the region of interest. In the present disclosure, a description based on TEM (or more appropriately quasi-TEM) propagation is satisfied provided that the transverse dimensions are small compared to the wavelength of the signal λ. For purposes of this disclosure, it is assumed that transverse dimensions are less than 0.1λ (about 1.5 mm at 0.13 μm technology). This value, however, is not limiting and other values may be possible.

For a signal wire operating in the rlc domain and in the presence of a ground plane, equation (1) is not always valid. A new set of equations has been derived by Davis and Meindl that accurately models such wires. See J. Davis and J. Meindl, Compact Distributed RLC Interconnect Models, IEEE Transactions on Electronic Devices, Vol. 47, No. 11, pp. 2068–2087, November 2000. Specifically, the equations show that for a signal wire operating in the rlc domain and in the presence of a ground plane, there exists a region (“Region I”) of resistance, inductance, and capacitance parameters (the “rlc parameters”) where the signal on the wire propagates at a speed nearly equal to the speed of light in the medium of the signal wire and where the wire exhibits “transmission-line” behavior. Transmission-line behavior is characterized by the propagation delay being linear with the length of the wire. The domain where this behavior occurs is where the rlc parameters satisfy the following inequality: $\begin{matrix} {{\frac{rL}{Z_{0}} \leq {2{\ln\left( \frac{4\; Z_{0}}{R_{tr} + Z_{0}} \right)}}},} & (3) \end{matrix}$ where ${Z_{0} = \sqrt{\frac{l}{c}}},$ l is the loop inductance per unit length of the wire, c is the total capacitance per unit length of the wire, r is the loop resistance per unit length of the wire, L is the length of the wire, and R_(tr) is the resistance of the signal source.

A constraint may be imposed to ensure that no damage occurs as a result of voltage overshoot in the wire. This constraint is met if the following inequality is satisfied: Z ₀ ≦R _(tr)  (4)

Thus, one can guarantee the minimization of propagation delay by using a wiring layout that satisfies the above inequalities such that the speed of propagation is nearly equal to the speed of light in the medium and transmission-line behavior is exhibited. A final physical constraint may also need to be considered because the physical parameters of the particular wiring layout (i.e., the lengths, widths, spacings, thicknesses, etc., of the wiring layout) must be capable of manufacture using current microlithography technology and must satisfy the TEM conditions described above.

II. The Clock Routing Problem

Fast-switching signals, such as the clock signal, are routed to multiple destinations within an integrated circuit. Because some signal paths are invariably longer than others, synchronizing the arrival time of the signals at their destinations becomes a major problem. Accordingly, clock trees having equal-length signal paths were devised to solve the synchronization problem. Clock trees are also one of the most important wire configurations that can operate in the rlc domain and benefit from signal delay minimization. Therefore, the synthesis method for controlling the delay in a wiring layout as shown and described herein uses a balanced clock tree as an exemplary wiring layout. It should be understood, however, that the disclosed method is not limited to the design of clock trees. The method, for example, may be applied to any wiring layout that operates at a sufficiently high frequency where inductance effects are appreciable.

Clock layouts are designed with two primary factors in mind: (1) the time required for a signal to propagate from a signal source to multiple destinations (the delay); and (2) the variance in the signal arrival times at the various destinations (the skew). Ideally, both factors are minimized so that a signal propagates to all elements in a region in a minimum of time with a minimum of skew. As noted above, a particular configuration of the clock tree may automatically minimize the skew, making delay minimization the only remaining factor to be resolved.

FIG. 1 shows a clock tree design for which skew is automatically minimized. Specifically, FIG. 1 shows a balanced H-tree 10 wherein each path from clock source to destination is of an equal length. A clock source 12 is located centrally within the tree 10. A series of six branches 14, extend from the source 12 and ultimately couple the source with multiple destinations, or “leaf nodes” (e.g., leaf node 16). The leaf nodes may be coupled with smaller grids of digital elements that are clocked by the clock signal. Typically, elements within the grids are so closely positioned to one another that any clock skew experienced within the grid is negligible. A branch of the clock layout may begin at either a signal source (e.g., a clock source 12, a repeater, a transistor, etc.) or a junction (e.g., junction 18). The junction may be a T-junction, as shown at the junction 18, or other multi-branched junction. A branch may terminate at either a leaf node, another junction, or other circuit element (e.g., repeater, transistor, etc.). Thus, for example, an exemplary branch 20 begins at the clock source 12 and ends at junction 22. Additionally, a clock tree has a certain “depth” associated with it corresponding to the number of branches a clock signal must propagate along to reach a leaf node from the clock source. In FIG. 1, for example, clock tree 10 has a depth of six because there are six branches a clock signal must propagate along before it reaches a leaf node from the clock source.

FIG. 2 shows a particular type of balanced H-tree known as a sandwich balanced H-tree (“SBHT”). Specifically, FIG. 2 shows four branches (or “sandwiches”) 14 of an SBHT clock tree terminating at eight leaf nodes 16. An SBHT is characterized by the presence of two parallel ground wires 32, 34 surrounding a signal wire 30, thereby forming a “sandwich-style” wiring layout. Ground wires 32, 34 are positioned on respective opposite sides of the signal wire 30 and are typically located at equal distances from signal wire 30. Ground wires 32, 34 serve as return paths for the current on signal wire 30. FIG. 2 also shows that the multiple leaf nodes 16 are each coupled with grids, shown generally at 36, which contain various other digital elements of the integrated circuit where the signal must arrive.

FIG. 3 is a cross-sectional view of a sandwich-style branch in an SBHT. Branch 14 has a signal wire 30 with a width w. Two opposing ground wires 32, 34 are located on respective opposite sides of signal wire 30, thereby “sandwiching” the signal wire. Each of the ground wires 32, 34 has a width g and an edge-to-edge wire separation s from signal wire 30. The size of wire separation s may be limited by physical design or manufacturing limitations. Accordingly, a minimum and a maximum value of s exist, denoted (s_(min), s_(max)), respectively. Both signal wire 30 and ground wires 32, 34 have a length L and a thickness h. Thickness h corresponds to the thickness of the metal layer of the integrated circuit in which the signal wire 30 and ground wires 32, 34 are located.

One attribute of a sandwich-style wiring layout is that the total value of each electrical parameter (loop resistance, loop inductance, and total capacitance) of any path from source to destination can be approximated as the sum of the electrical parameters of the path segments that form it. Thus, one can evaluate the electrical parameters of each branch of an SBHT independent of the other branches. More specifically, for a path P(I, D_(i))={I=N₀, N₁, . . . , N_(n)=D_(i)} from clock input I to one of multiple destinations D_(i), where i=1, . . . , 2^(n−1), $\begin{matrix} \begin{matrix} {{L \cdot {r_{loop}\left( {P\left( {I,D_{i}} \right)} \right)}} = {\sum\limits_{j = 1}^{n}{L_{j}{r_{loop}\left( \left\{ {N_{j - 1},N_{j}} \right\} \right)}}}} \\ {{L \cdot {l_{loop}\left( {P\left( {I,D_{i}} \right)} \right)}} = {{\sum\limits_{j = 1}^{n}{L_{j}{l_{loop}\left( \left\{ {N_{j - 1},N_{j}} \right\} \right)}}} + ɛ}} \\ {{L \cdot {c_{tot}\left( {P\left( {I,D_{i}} \right)} \right)}} = {{\sum\limits_{j = 1}^{n}{L_{j}{c_{tot}\left( \left\{ {N_{j - 1},N_{j}} \right\} \right)}}} + {ɛ^{\prime}.}}} \end{matrix} & (5) \end{matrix}$ The value ε corresponds to the summation of mutual inductances of orthogonal and/or far-separated circuits, rendering the correction negligible. Likewise, the most relevant contribution to ε′ comes from capacitance effects at the T-junctions, whose dimensions are small enough to be neglected.

Another attribute of a sandwich-style wiring layout is that the loop inductance of the signal wire 30 with ground wires 32, 34 as return paths can be controlled by altering the parameters of the design. For instance, the wire separation s between signal wire 30 and ground wires 32, 34 or the ground wire width g can be altered individually or in combination to change the loop inductance. The total capacitance of the layout is dependent on wire separation s. The loop resistance of the layout, however, is dependent on the ground wire width g, but not the wire separation s.

The adjustment of the rlc parameters of a sandwich-style wiring layout by altering the wire separation s and wire width g has consequences for the time delay of the signal. For instance, for a given sandwich-style wiring layout where all parameters are fixed except for wire separation s, a set of wire separations s can be found that allow the wiring layout to operate in Region I (discussed above in the General Considerations section). Similarly, for a given layout where all parameters but ground wire width g are fixed, a set of ground wire widths g can be found that allow the layout to operate in Region I.

III. The General Method of Configuring a Wiring Layout

FIG. 4 is a flowchart showing a method for configuring a sandwich-style wiring layout by varying the wire separation s such that the wiring layout exhibits signal propagation at nearly the speed of light in the medium of the signal wire and exhibits transmission-line behavior. It is understood that the method could be modified for calculating the corresponding set of any other of the physical parameters of the wiring layout that affect rlc values. The sandwich-style wiring layout comprises a signal wire with two opposing parallel ground wires, as described above. The wiring layout may constitute an entire wiring layout from a signal source to a destination. Alternatively, the wiring layout may comprise a single branch of a SBHT, which, as noted above, can be analyzed separately from the other branches. In process block 40, the physical parameters of a sandwich-style wiring layout are provided. The physical parameters may include the signal wire width w, metal layer thickness h, ground wire width g, and wire length L. In process block 41, the loop resistance of the wiring layout is calculated. In process block 42, the loop inductance of the wiring layout is represented as a function of wire separation. The loop inductance of the layout is determined using the other physical characteristics of the layout as fixed parameters and the wire separation as the only variable. The loop inductance of the layout is a linear combination of the partial self inductance of each wire and the partial mutual inductance between each pair of wires. The inductance effects can be calculated using the simplified expressions discussed below. In process block 44, the capacitance of the wiring layout is represented as a function of wire separation. Like inductance, the capacitance of the layout is determined using the other physical characteristics of the layout as fixed parameters and the wire separation as the only variable. As more fully described below, to solve for the capacitance of the layout, function approximation techniques that perform data fitting to 3-D simulation results may be used. For instance, a nonlinear least square method may be used. In process block 46, a set of wire separations is found such that the corresponding wiring layout operates in Region I while preventing voltage overshoot. The process of calculating this set is more fully explained below with reference to FIG. 6. In process block 48, a single wire separation is selected from this set of wire separations, and the layout is configured using the selected wire separation. The process of selecting a wire separation is more fully explained below with reference to FIG. 16.

A. Calculating the rlc Parameters

1. The rlc Parameters Generally

A tree of depth n is composed of 2^(n)−1 sandwiches. The equivalent serial circuit of a sandwich configuration (a line with a return ground plane) can be obtained using circuit algebra. FIG. 5 shows two circuits equivalent to the sandwich configuration. Specifically, circuit diagram 50 shows an equivalent circuit with each circuit element displayed. For instance, l_(s,g) is the mutual inductance between the signal wire s and one of the ground wires g. Circuit 52, on the other hand, shows an equivalent circuit with only the resistance and inductance of the loop displayed.

The equivalent loop resistance per unit length is given by: $\begin{matrix} {{r_{loop} = {r_{s} + \frac{r_{g}}{2}}},} & (6) \end{matrix}$ where r_(s) and r_(g) are the resistance per unit of length of the signal wire and ground wires, respectively. As explained above, the total equivalent resistance is separable and given by the sum of the total equivalent resistances for each partition.

To compute the equivalent loop inductance per unit length for one sandwich of the SBHT tree, reference should be made to FIG. 5. The resulting l_(loop) can be immediately inferred: $\begin{matrix} {{l_{loop} = {l_{s} - {2l_{s,g}} + {\frac{1}{2}l_{g,g}} + {\frac{1}{2}l_{g}}}},} & (7) \end{matrix}$ where l_(s) and l_(g) are the partial self inductances of the signal wire and the ground wires, respectively. The values l_(s,g) and l_(g,g) refer to the partial mutual inductances of the signal wire with the ground wires and the ground wires with the ground wires, respectively. The separability into multiple independent configurations (i.e., the application of the cascade rule to the configuration) can be verified using an inductance simulation program such as FastHenry, which is available from the Massachusetts Institute of Technology.

The equivalent capacitance per unit length of a sandwich c_(tot) is given by: c _(tot)=2c _(s,g) +c _(r),  (8) with c_(s,g) the mutual capacitance between one ground wire and the signal wire, and c_(r) the sum of the capacitances of the signal wire to the substrate and to other wires not participating in the return path. As mentioned before, the total equivalent capacitance of the signal path from source to destination is separable and given by the sum of the total equivalent capacitances of each partition. Errors due to mutual coupling between partitions are negligible.

The problem now becomes one of computing accurately the r_(loop), l_(loop), c_(tot), parameters that correspond to the r, l, and c values that enter in the transmission-line equation (3). As noted above, the computation is made as a function of the physical parameters: L, w, h, g and s (see FIG. 3).

2. Resistance

In this section, a method is described for calculating the resistance as may be used in process block 41 of FIG. 4. The resistance per unit length for a straight wire is given by the simple expression: $\begin{matrix} {{r = \frac{1}{\sigma\;{wh}}},} & (9) \end{matrix}$ with σ the conductivity of the metal, w the width of the wire, and h the thickness of the wire. The results are inserted in equation (6) for both r_(s) and r_(g).

3. Inductance

In this section, a method is described for calculating inductance as may be used in process block 42 of FIG. 4. The calculation of the loop inductance for the configuration of interest, the sandwich configuration, can be obtained from the general expression for the partial mutual inductance (

) of two filaments i, j: $\begin{matrix} {{\mathcal{L}_{i,j} = {\frac{\mu_{0}}{4\;\pi}{\int{\int{\frac{1_{i} \cdot 1_{j}}{{\overset{->}{x} - {\overset{->}{x}}^{\prime}}}{\mathbb{d}s^{\prime}}{\mathbb{d}s}}}}}},} & (10) \end{matrix}$ with μ₀ the permeability of the vacuum, I the unit vector in the direction of the current, and the denominator of the integral the distance between two points in the wires. The integrals are extended over the lengths of the filaments. Furthermore, integrating the above expression over the transverse area occupied by the two conductors, and dividing by the product of the total cross sectional areas, leads to the following close-form solution for the partial mutual inductance of two wires of rectangular cross-section of the same length L: $\begin{matrix} {{\mathcal{L}_{mutual} = {\frac{\mu_{0}L}{2\;\pi}\left\lbrack {{\ln\left( {\frac{L}{d} + \sqrt{1 + \frac{L^{2}}{d^{2}}}} \right)} - \sqrt{1 + \frac{d^{2}}{L^{2}}} + \frac{d}{L}} \right\rbrack}},} & (11) \end{matrix}$ with d the geometric mean distance (GMD) between the two wires. The GMD of two wires of the same length is given by: $\begin{matrix} {{{\ln\left( {GMD}_{A,B} \right)} = {\frac{1}{A \times B}{\int_{y1}^{y2}{\int_{z1}^{z2}{\int_{y3}^{y4}{\int_{z3}^{z4}{\ln\sqrt{\left( {y - y^{\prime}} \right)^{2} + \left( {z - z^{\prime}} \right)^{2}}{\mathbb{d}z^{\prime}}{\mathbb{d}y^{\prime}}{\mathbb{d}z}{\mathbb{d}y}}}}}}}},} & (12) \end{matrix}$ with A=w₁×(z₂−z₁) and B=w₂×(z₄−z₃), the areas of the cross-sections. The geometry is explained in FIG. 6. FIG. 6 shows a first wire 54 and a second wire 56 and the geometrical parameters of equation (12) that define their relation to one another.

To calculate the partial self inductance of a wire of rectangular cross-section, the same equation (11) applies. The GMD of a single wire of area w×h is well approximated by: ln(d)=ln(w+h)−3/2.  (13) See F. Grover, Inductance Calculations Working Formula and Tables, Instrument Society of America, 1945. As shown in FIG. 7, the result of using equations (11) and (12) for computing partial self inductance of rectangular wires is accurate to within 1% when compared to 3-D simulations with FastHenry for isolated lines in the frequency domain of interest. The method is also computationally efficient. Some corrections may apply when neighboring wires are sufficiently close (see the “additional consideration” section below)

For partial mutual inductance, the following approximation to the GMD of two wires with identical rectangular cross-section and equal length is used: ln(GMD)=ln(a)+ln(k)  (14) with a the center-to-center distance between the wires and ln (k) a tabulated correction value.

To compute the GMD of two wires of the same length and the same thickness, but with different widths (FIG. 8(A)), the wire with maximum width (wire B) is partitioned into n=└B/A┘ pieces of area B_(i)=A, for i=1, . . . ,n and a remaining piece of area B_(n+1) (FIG. 8(B)). The following proposition permits the original GMD to be approximated using the formula for equal cross-sections: given a situation as in FIG. 8(B), it follows that $\begin{matrix} {{\ln\left( {GMD}_{A,B} \right)} = \frac{{A{\sum\limits_{i = 1}^{n}\left( {\ln\left( {GMD}_{A,B_{i}} \right)} \right)}} + {B_{n + 1}{\ln\left( {GMD}_{A,B_{n + 1}} \right)}}}{{n\; A} + B_{n + 1}}} & (15) \end{matrix}$ The proof of the proposition follows directly from equation (12). In equation (15), all but the last term correspond to calculations of GMD of wires of equal cross-section. To compute GMD_(A,B) _(n+1) recursion with the same equation (15) may be used, but with A changed to B_(n+1) and B changed to A. Recursion continues until the last remaining term is of negligible or zero size. It has been verified that a recursion depth of four suffices to achieve an upper bound of 1% of error in the computation of the partial mutual inductance for realistic configurations. This small amount of error is shown in FIG. 9, which displays a comparison between results obtained using FastHenry and the simplified expression. The final step is to combine the different terms into equation (7). This completes the accurate computation of loop inductance in terms of the physical parameters. The resulting code is computationally efficient, while maintaining the precision of the 3-D-simulator FastHenry.

4. Capacitance

In this section, a method is described for calculating capacitance as may be used in process block 44 of FIG. 4. The capacitance value c that enters in the optimization problem is the total capacitance of the signal line. This is the sum of the values of mutual capacitances with the ground neighbors c_(s,g1) and c_(s,g2) plus the sum of the cross-coupling capacitances to the wires in lower layer(s) plus the capacitance to the substrate, which is termed c_(r). Given the symmetry of the problem: c _(s,g) :=c _(s,g1) =c _(s,g2),  (16) there are no closed-form expressions for the capacitance. Thus, an efficient and accurate method to calculate c_(tot) for different geometrical configurations is needed. Function approximation techniques may be used that perform data fitting to 3-D simulation results. The data fitting process is the result of a nonlinear least square fit. The capacitance of the signal wire with respect to its neighbor (c_(s,g)), and its capacitance with respect to the layer beneath plus the capacitance with the substrate (c_(r)) are considered separately. For fitting purposes, three-dimensional simulations performed with ICARE may be used. ICARE is available through LETI, France. The following functional form for the mutual capacitance between the signal wire and one of its ground neighbors may be used: $\begin{matrix} {{{c_{s,g}\left( {s,w} \right)} \approx {\left( {{\beta_{1}{\mathbb{e}}^{{- {\alpha 1}}\frac{s}{s_{\min}\;}}} + {\beta_{2}\left( \frac{s}{s_{\min}} \right)}^{- \alpha_{2}}} \right)\left( \frac{w}{w_{\min}} \right)^{\alpha_{3}}}},} & (17) \end{matrix}$ with s_(min) and w_(min) the minimum separation and width allowed by the technology. Fitting equation (17) to a given set of observations is handled as a nonlinear least square problem.

The variables separate in the following fashion: c _(s,g)(s,w)≈c ₁(s)*c ₂(w),  (18) thus permitting two independent least square problems. First, a uniform distributed collection of values of variable s, s={s₁,s₂, . . . , s_(n)} is selected. Then, the respective observation values y_(i=c) _(s,g)(s_(i), w=w_(min)) are obtained using ICARE.

The values β=(β₁,β₂) and α=(α₁,α₂) must be found that minimize the nonlinear functional: $\begin{matrix} {{r\left( {\beta,\alpha} \right)} = {\sum\limits_{i = 1}^{n}{\left\lbrack {y_{i} - {c_{1}\left( {\beta,{\alpha;s_{i}}} \right)}} \right\rbrack^{2}.}}} & (19) \end{matrix}$ To compute α₃, a value of s=s_(k) is fixed and a data set is generated by performing simulations for w={w₁, w₂, . . . , w_(m)}. The resulting observations are called y_(i)−c_(s,g)(s_(k), w_(i)). The problem becomes one of fitting the data (w_(i), y_(i)) to the equation $\begin{matrix} {{c_{s,g}(w)} = {{c_{1}\left( s_{k} \right)}{\left( \frac{w}{w_{\min}} \right)^{\alpha 3}.}}} & (20) \end{matrix}$ The nonlinear least square method is reapplied to obtain α₃.

The program VARPRO, which is available from Stanford University, may be used to find the values of the linear and nonlinear parameters that are optimal in the least square sense. FIGS. 10 and 11 display the fits. The equivalent capacitance to other layers not participating in the return path of the currents but contributing to the total capacitance of the signal line is mimicked with that of a single line running orthogonal to the signal and having a ground plane below. The magnitude is only weakly dependent on s and g for fixed w. Thus, it is allowable to perform, with little loss in precision, an average in s and g to represent c_(r).

B. Determining the Solution Interval of Wire Separations

FIG. 12 is a flowchart showing a method for determining the solution interval of wire separations in a wiring layout as may be used in process block 46 in FIG. 4. In process block 70, a minimum wire separation s′ is determined at which an rlc relationship is created in the wiring layout such that it operates in Region I. Wire separation s′ is calculated by redefining equation (3) as a functional F where: $\begin{matrix} {F = {\frac{rL}{Z_{0}} - {2{\ln\left( \frac{4Z_{0}}{R_{tr} + Z_{0}} \right)}}}} & (21) \end{matrix}$ and searching for the value of s where F=0 using the functions for inductance and capacitance derived in process blocks 42 and 44 of FIG. 4. The value of s for which F=0 corresponds to s′. Functional F is monotonically decreasing with s, which assures that if s>s′ then F(s)≦0. Therefore, the value s′corresponds to the left side of the solution interval.

In process block 72, a maximum wire separation s′ is determined at which an rlc relationship is created enabling the wiring layout to operate in Region I. Wire separation s″ corresponds to the right side of the solution interval. Wire separation s″ is calculated by redefining the overshoot restriction given in equation (4) as a functional P where: P=Z ₀ −R _(tr)  (22) and searching for the value of s where P=0. Functional P is monotonically increasing with s, this assures that for s<s″, with P(s″)=0 then P(s)≦0. The solution interval, if it exists, is then s ∈[s′,s″].

In order to find F=0 and P=0, Newton's method to solve systems of nonlinear equations is used. Since Newton's method is locally convergent, the bisection method is performed to the first iterates in order to assure convergence from any point. This is well known as a global convergent version of Newton's method. The system of non linear equations to be solved is: $\begin{matrix} {\begin{pmatrix} {F\left( s^{\prime} \right)} \\ {P\left( s^{''} \right)} \end{pmatrix} = {\begin{pmatrix} 0 \\ 0 \end{pmatrix}.}} & (23) \end{matrix}$

At process block 74, a determination is made as to whether s″ is greater than s′. This determination is done to ensure that a feasible set of wire separations exists. If s″ is greater than s′, then a feasible set of optimal wire separations exists, which is output at process block 78. If s″ is less than s′, then no feasible set of optimal wire separations exist and this fact is output at process block 76. If no feasible set of optimal wire separations exist, then the other physical parameters of the wiring layout may have to be changed to allow for the wiring layout to operate in Region I.

The process described above may be summarized as follows. To find the solution interval for variable s, for a fixed value of g, two values of s: s=s_(F), s_(P) where F(s_(F))=0, P(s_(P))=0 are searched. The solution interval for s where the restrictions F(s)≦0 and P(s)≦0 are simultaneously satisfied, if it exists, is the intersection of the following two intervals: [s_(F), λ/10) and [s_(min), s_(P)]. The upper bound λ/10 is the limit of validity of the transmission-line representation.

FIG. 13 is a flow chart identical to FIG. 12, but shows the relevant processes in terms of their mathematical equivalents. In process block 90, the value of s for which functional F is equal to zero is determined. This value is termed S′₀ and corresponds to the lower bound of the set of optimal wire separations. In process block 92, the value of s for which functional P is equal to zero is determined. This value is termed S″₀ and corresponds to the upper bound of the set of optimal wire separations. At process block 94, it is determined whether S″₀ is greater than S′₀. In other words, it is determined whether the value calculated as the upper bound is greater than the value calculated for the lower, and thus whether a set of acceptable values of s exist. If S″₀ is greater than or equal to S′₀, then a set of optimal wire separations is feasible, and this set is output at process block 98. If, however, S″₀ is less than S′₀, then a set of optimal wire separations is unfeasible, and this result is output at process block 96.

The particular method described with respect to FIGS. 4 through 13 of varying wire separation s to achieve the desired rlc parameters in the wiring layout is not intended to be limiting in any way. The method disclosed may be modified by one of ordinary skill in the art so that any one of the physical parameters affecting the inductance of the wiring layout may be optimized to achieve the desirable effects discussed above. For instance, the method may be modified such that an optimal ground wire width g is calculated that allows the wiring layout exhibit transmission-line behavior with signal propagation at approximately the speed of light in the medium of the signal wire. When the ground wire width g is the independent variable, simulations with FastHenry have shown that Z₀ as a function of g displays a single minimum (see FIG. 14). Further, F as function of g has at most one point where it vanishes. The interval for g where F≦0, if it exists, is [g_(F), λ/10), with g_(F) the value of g where F vanishes. As shown in FIG. 14, P as a function of g has at most two vanishing points. To find the relevant interval of g, the zeros of P can be found, if they exist, and then the intervals where P(g)≦0 can be found by inspection.

FIG. 15 shows an exemplary table produced from the method described above. The table shows the results for various possible sandwich-style wiring layouts. The solutions include sets of optimal wire separations s and sets of optimal ground wire widths g. Column 110 displays the ID number of a particular configuration of line length L, resistance of the driver R_(tr), and signal wire width w. Column 112 displays two sets of optimal wire separations s for each ID number. The first set, shown generally at 114, is the set of optimal wire separations for a ground wire width of 6 μm. The second set, shown generally at 116, is the set of optimal wire separations for a ground wire width of 8 μm. Also shown are sets of optimal ground wire widths calculated for two fixed wire separations. Column 118 displays the two sets of optimal ground wire widths g for each ID number. The first, shown generally at 120, is the set of optimal ground widths for a wire separation of 2 μm. The second set, shown generally at 122, is the set of optimal ground wire widths for a wire separation 5 μm. Thus, for example, for ID number 1, the wire length L for all three of the wires in the layout is 2500 μm, the driver circuit has R_(tr)=100 Ohms, and the width of the signal wire w is fixed at 6 μm. For a wire separation between the edge of the signal wire and the edge of either ground wire of 2 μm, there is a continuum of solutions shown in column 118 for the width of the ground wire g starting at 5.3 μm and ending at 59.0 μm. For a wire separation of 5 μm, however, there are no feasible solutions, which is denoted by (*,*) Additionally, some configurations shown have a solution of optimal ground wire width with an upper limit bounded by 0.1λ, where λ is the wavelength of the electromagnetic signal propagating on the signal line, which is denoted by (−).

C. Selecting a Wire Separation from the Solution Interval

FIG. 16 shows a method of selecting a wire separation from the solution interval of wire separations as may be used in process block 48 of FIG. 4. In process block 130, the smallest possible wiring separation is selected from the solution interval of wire separations (s′, s″), i.e. s′. In process block 132, the wiring layout is tested using the smallest possible wiring separation selected. This testing may be performed using a 3-D simulator configured to test the layout at the maximum frequency of interest. In process block 134, the smallest possible wiring separation is updated if the testing at process block 132 determines that the wiring layout was not acceptable. This update may adjust the physical parameters of the wiring layout to account for certain frequency-dependent effects. Specifically, well-understood phenomena, such as the proximity effect, skin effect, and dielectric relaxation, can affect the rlc parameters of the layout. These effects are discussed in greater detail below.

IV. Possible Corrections

A. Rise Time Corrections

Davis and Meindl derived the following expression for V_(fin)(x,t), which is the output solution to a Heaviside pulse: $\begin{matrix} {\begin{matrix} {{V_{fin}\left( {x,t} \right)} = {{2{V_{\inf}\left( {x,t} \right)}} + {2V_{dd}\frac{Z_{0}}{Z_{0} + R_{tr}}{\mathbb{e}}^{{- \sigma}\; t}{\sum\limits_{n = 1}^{q}{\sum\limits_{i = 0}^{n}{\sum\limits_{j = 0}^{\infty}{\frac{{n\left( {n - 1 + j} \right)}!}{{i!}{j!}{\left( {n - i} \right)!}}\left( {- 1} \right)^{i}\Gamma^{n - i + j} \times}}}}}}} \\ {\begin{Bmatrix} {{\left( \frac{t - {\left( {{2n} + 1} \right)x\sqrt{lc}}}{t + {\left( {{2n} + 1} \right)x\sqrt{lc}}} \right)^{{({i + j})}/2}{I_{i,{+ j}}\left( {\sigma\sqrt{t^{2} - \left( {\left( {{2n} + 1} \right)x\sqrt{lc}} \right)^{2}}} \right)}} +} \\ {\frac{1}{1 - \Gamma}{\sum\limits_{k = 1}^{\infty}{\left( \frac{t - {\left( {{2n} + 1} \right)x\sqrt{lc}}}{t + {\left( {{2n} + 1} \right)x\sqrt{lc}}} \right)^{{({i + j + k})}/2}{I_{i + j + k}\left( {\sigma\sqrt{t^{2} - \left( {\left( {{2n} + 1} \right)x\sqrt{lc}} \right)^{2}}} \right)}\left( {4 - {\left( {1 + \Gamma} \right)^{2}\Gamma^{k - 1}}} \right)}}} \end{Bmatrix} \times} \\ {u_{0}\left( {t - {\left( {{2n} + 1} \right)x{\sqrt{\left. {lc} \right)}.}}} \right.} \end{matrix}{where}} & (24) \\ {{q = \left\lfloor {0.5\left( {\frac{t}{x\sqrt{lc}} + 1.0} \right)} \right\rfloor}{{with},}} & (25) \\ {{{V_{\inf}\left( {x,t} \right)} = {V_{dd}\frac{Z_{0}}{Z_{0} + R_{tr}}{\mathbb{e}}^{{- \sigma}\; t} \times \begin{Bmatrix} {{I_{0}\left( {\sigma\sqrt{t^{2} - \left( {x\sqrt{lc}} \right)^{2}}} \right)} +} \\ {\frac{1}{1 - \Gamma}{\sum\limits_{k = 1}^{\infty}{\left( \frac{t - {x\sqrt{lc}}}{t + {x\sqrt{lc}}} \right)^{\frac{k}{2}}{I_{k}\left( {\sigma\sqrt{t^{2} - \left( {x\sqrt{lc}} \right)^{2}}} \right)}\left( {4 - {\left( {1 + \Gamma} \right)^{2}\Gamma^{k - 1}}} \right)}}} \end{Bmatrix} \times {u_{0}\left( {t - {x\sqrt{lc}}} \right)}}},} & (26) \end{matrix}$ with Γ=(R_(tr)−Z₀)/(R_(tr)+Z₀), σ=r/(2l), I_(k)(−) the modified Bessel function of order k-th.

As used herein, V_(DM)(t):=V_(fin)(L,t). From general theorems of linear partial differential equations it is well known that the output V_(out)(t) for a general input signal I(t) is given by: $\begin{matrix} {{V_{out}(t)} = {\frac{\mathbb{d}\;}{\mathbb{d}t}{\left( {{V_{DM}(t)}*{I(t)}} \right).}}} & (27) \end{matrix}$ The operator “*” is the convolution product: $\begin{matrix} {{{f(t)}*{g(t)}} = {\int_{- \infty}^{\infty}{{f(\tau)}{g\left( {t - \tau} \right)}{{\mathbb{d}\tau}.}}}} & (28) \end{matrix}$ Consider for I(t) the form: $\begin{matrix} {{I(t)} = \left\{ \begin{matrix} {{0{~~~~~~~~~~~~}{if}\mspace{14mu} t} \leq \; 0} \\ {{\frac{t}{T_{rise}}{~~~~}{if}\mspace{14mu} 0} < t \leq \; T_{rise}} \\ {{1{~~~~~~~~~~~~}{if}\mspace{14mu} t} > {T_{rise}.}} \end{matrix} \right.} & (29) \end{matrix}$ The response V_(out) to I becomes (from equation (27)): $\begin{matrix} {{V_{out}(t)} = {\int_{- \infty}^{\infty}{{V_{DM}(\tau)}\frac{\mathbb{d}{I\left( {t - \tau} \right)}}{\mathbb{d}t}{{\mathbb{d}\tau}.}}}} & (30) \end{matrix}$ The derivative of I(t−τ) is equal to 1/T_(rise) for t−T_(rise)<τ<t and is zero elsewhere. Therefore, $\begin{matrix} {{V_{out}(t)} = {\frac{1}{T_{rise}}{\int_{t - {Trise}}^{t}{{V_{DM}(\tau)}\ {{\mathbb{d}\tau}.}}}}} & (31) \end{matrix}$ The parameters in equation (24) are taken such that the configuration is in Region I, and numerical integration with equation (31) is performed. Results are shown in FIG. 17. Notice that V_(out)(t) has a discontinuity in its first derivative at a point p that will be identified. For this purpose, the first derivative of V_(out) is examined by differentiation of equation (31): $\begin{matrix} {{\frac{\mathbb{d}{V_{out}(t)}}{\mathbb{d}t} = {\frac{1}{T_{rise}}\left\lbrack {{V_{DM}(t)}\  - {V_{DM}\left( {t - T_{rise}} \right)}} \right\rbrack}}\ ,} & (32) \end{matrix}$ It has its first two discontinuities at t=t_(f) and t=t_(f)+T_(rise), since V_(DM) has a discontinuity at t=t_(f). It can then be concluded that: p=t_(f)+T_(rise).

From equation (31): $\begin{matrix} {{V_{out}\left( {t_{f} + T_{rise}} \right)} = {\frac{1}{T_{rise}}{\int_{tf}^{{tf} + {Trise}}{{V_{DM}(\tau)}\ {{\mathbb{d}\tau}.}}}}} & (33) \end{matrix}$ The linear approximation for V_(DM)(t) in t ∈(t_(f), t_(f)+T_(rise)) is taken. From the mean value theorem, it follows that: $\begin{matrix} {{V_{out}\left( {t_{f} + T_{rise}} \right)} \approx {{V_{DM}\left( {t_{f} + \frac{T_{rise}}{2}} \right)}.}} & (34) \end{matrix}$ The result is exact in the linear approximation.

Consider now the linear approximation to V_(out)(t) in the same interval: $\begin{matrix} {{V_{out}(t)} \approx {\frac{V_{DM}\left( {t_{f} + {T_{rise}/2}} \right)}{T_{rise}}{\left( {t - t_{f}} \right).}}} & (35) \end{matrix}$ Impose V_(out)(t)=0.5V_(dd), which is feasible since solutions in Region I were taken, and obtain: $\begin{matrix} {{t_{50\%} = {t_{f} + {\frac{T_{rise}}{2}\left( \frac{V_{dd}}{V_{DM}\left( {t_{f} + {T_{rise}/2}} \right)} \right)}}},} & (36) \end{matrix}$ which is the new expression for the 50% time delay. Equation (36) improves significantly over the naive shift in the delay computation t=t_(f+T) _(rise)/2. The expression has been derived for T_(rise)<4t_(f), since at this point new discontinuities appear in V_(DM)(t).

It has been verified numerically that the relative error incurred in the delay calculation, resulting from the linear approximations presented above, is very small for T_(rise)≦2t_(f). The error increases with T_(rise), and for T_(rise)=2t_(f) is a reasonable 3%. The error becomes large by the time the upper limit T_(rise)=4t_(f) is reached. Transmission-line behavior, which is identified with equation (36), demands: T _(rise)≦2√{square root over (lc)}L.  (37) Equation (36) is a solution to the delay estimate for a signal in Region I for T_(rise)<2t_(f).

Fixing T_(rise) in equation (36), the L dependence displays both linear and quadratic behavior, at variance with the zero rise time solution. It is a second bound for a signal in Region I and makes the quadratic term negligible. A subsidiary consequence of finite T_(rise) is the relaxation of the overshoot constraint Z₀≦R_(tr). Corrections due to a finite clock period in equation (36) are negligible for a clock period of reasonable bandwidth (a clock period larger than 6T_(rise).)

B. Corrections for Frequency-Dependent Effects

In general, rlc parameters are frequency dependent in accordance with well-understood phenomena: proximity, skin effect, and dielectric relaxation. The range of frequencies that are of concern is determined by the rise time of the signal. The frequency spectrum will contain appreciable content up to a frequency given by: $\begin{matrix} {f_{\max} = {\frac{1}{{\pi\; T_{rise}}\;}.}} & (38) \end{matrix}$ This is the view of the T_(rise)-related phenomena in terms of the Laplace coordinates. The rise time T_(rise) is determined by technology and circuit considerations. For example, technology may determine the transistor delay to be τ_(tr)≈2 ps at 130 nm. The T_(rise) of the signal is determined by the underlying logic feeding the line. For example, T_(rise) may be approximately 30 ps at 130 nm. Based on these exemplary numbers and equation (38), the signal spectrum will be appreciable up to a maximum frequency O(10) GHTz. Using these figures, possible corrections to the constant r and l assumption to account for the skin effect and the proximity effect are considered.

The parameter that controls the skin effect is the magnetic field penetration on the metal δ, which results from one-dimensional solutions to Maxwell's equations on a conductor media and is given by: $\begin{matrix} {\delta = {\sqrt{\frac{1}{\mu_{0}f\;\sigma}}.}} & (39) \end{matrix}$ To minimize its influence, meaning full penetration of the magnetic field on the metal and as such uniform current distribution, the thickness of the metal layer h is taken as h<2δ with δ≈0.7 μm for Cu at 10 GHTz. One-dimensional treatment of skin depth is not completely persuasive in two dimensions. Therefore, the consistency is checked via accurate simulations. There also exists the simultaneous need to minimize r, which itself calls for thicker h. Thus, a compromise of h≈δ is used. In this example, h is set to 650 nm. Simulations run using FastHenry have verified that skin effect corrections are in fact negligible up to 10 GHTz. With regards to c, the frequency regime where dielectric response times are comparable to the rise times of signals is above the region of interest.

Another factor responsible for frequency variation of the parameters is the proximity effect. Its main effects are to increase r and decrease l as a function ƒ. The modifications to the constant parameter assumption can be significant for wide wires separated by short distances. The partial-self-inductance contribution is the most sensitive to proximity effects, since the current on each wire tends to redistribute towards the surfaces closer to the neighbor wires. The classic quasi-static treatment discussed above in section III.A.1 may be replaced by FastHenry simulations. For example, the partial self inductance for wires described in FIG. 15 can decrease up to 4% from the quasi-static values. The variation in mutual inductance is less than 1% for the entire configuration represented in FIG. 15. As a consequence of these two effects, table 1 shows that the loop inductance can decrease to a maximum of 6% for frequencies up to 10 GHTz.

TABLE 1 % Decrease in l From Quasi-Static to 10 GHTz. (h = 0.65 μm, w = 10 μm, s = max{w,g}) g (in μm) % decrease in l 10 5.1% 15 5.2% 30 4.9% 50 4.5%

As shown in table 2, the r variation due to the same physical effect is larger than the corresponding reactance variation.

TABLE 2 % Decrease in r From Static Value to 10 GHTz. g (in μm) % increase in r 10 25% 15 26% 30 26% 50 25%

The net result on the solution space is that an increase of r(ω) and a decrease of l(ω) makes inequality (3) more restrictive.

The impact on the solution intervals when proximity effects are included can be verified using FastHenry. Specially, using a collection of configurations from FIG. 15 and their respective solution intervals of s, FastHenry can be used to compute the parameters r and l for a given value of s in the interval at the maximum frequency considered, 10 GHTz. The resulting parameters can then be analyzed to determine if inequality (3) is satisfied.

The net modification for a given interval in s, (s₁, s₂), and given w and g, is to increase s₁ so as to compensate for the increase in r and the decrease in l. Naturally the effect is more pronounced for longer wires. Table 3 shows the modified results.

TABLE 3 Renormalization of s₁ (from FIG. 15) When Proximity Effects are Considered (g = 6 μm) ID old s₁ (in μm) new s₁ (in μm) 1 0.28 0.33 7 0.37 0.56 13 0.71 1.8

Notice that the existence and nature of the solution space does not change. Solutions exist in the presence of proximity effects for lengths on the cm scale. The absolute value of the upper limit depends on specific details of the technology, and the particular wires under consideration. The lower limits, on the other hand, are exclusively dictated by equation (37), which only depends on the technology, L≦1 mm for 130 nm.

V. Reflections

A. Reflections in General

The principles of the method discussed above may also be used to help minimize some of the deleterious effects that are inherent in signal propagation in an SBHT. Specifically, the physical parameters of the wire layout may be altered to minimize reflections of the signal that are caused by discontinuities in the signal line. In a SBHT, reflections occur at the junctions of the tree where an upstream branch is coupled in parallel with downstream branches. The magnitude of the reflection is determined by the difference between signal line impedances at the junction. Thus, to eliminate the effects of reflection, the impedance of the downstream branches should be matched with the impedance of the upstream branch. As discussed above, the impedance of a branch in a SBHT is a function of the rlc parameters of the wiring layout and can be altered by modifying the physical parameters of the layout design. Thus, by adjusting the appropriate physical parameters of downstream SBHT branches to match the impedance of an upstream branch, it is possible to minimize the effects of reflections. This process can be performed iteratively on multiple downstream branches to minimize reflection effects throughout a series of branches in an SBHT. At the deeper levels of the tree, however, the physical parameters required to match the impedance of the original branch might become unacceptably large. Thus, the insertion of a repeater may be required to restore the signal to its original voltage value.

B. Impedance Matching

Given a SBHT of depth n. The magnitude of the reflection at each junction is determined by the impedance mismatch at the boundary. Because the junction of a SBHT has two downstream branches coupled in parallel to an upstream branch, to equalize the impedance, and thus eliminate reflections, each one of the downstream branches must have: Z _(i)=2Z _(i−1)= . . . =2^(i) Z ₀ for i=1, . . . , n  (40) where the subindex i characterizes the depth of the tree. Now, $\begin{matrix} {{Z_{i} = {Z_{i,0}\sqrt{\frac{p + \frac{r_{i}}{l_{i}}}{p}}}},} & (41) \end{matrix}$ with ${Z_{i,0} = \sqrt{\frac{l_{i}}{c_{i}}}},$ and p the Laplace complex variable.

The following high frequency approximation is made: Z_(i)≈Z_(i,0). This is an accurate approximation for the high frequency part of the impedance. Since p=j2πf_(max) with f_(max≈)10 GHTz, the error in the approximation is small. The impedance is matched based on its high frequency component, since it is the high frequency regime that is the one responsible for the linear time-of-flight behavior of the delay (in other words the small t behavior). For routing purposes, common w and g on all branches are maintained, (i.e., r is the same for all branches). Notice that at the junctions, equation (40) does not need to be satisfied for resistance matching.

To minimize reflections for fixed w and g, s_(i) is varied from one level of the tree to the next in such a way as to satisfy equation (40). The modification demanded by impedance matching on the previous analysis translates into an iterative process, which is explained in greater detail below with reference to FIG. 18. The first step consists of choosing a driver's strength R_(tr) feeding the main branch and finding its solution interval (s_(0,1), s_(0,2)). Then, choosing a value s₀ belonging to this interval and subsequently finding the values of s_(i) for the remaining levels using equation (40). Notice that the appropriate L_(n) that enters into the equation is the sum of the Ls corresponding to the father plus those corresponding to the sons up to the leaf.

The length L_(n) is calculated using the following expression: $\begin{matrix} {{L_{n} = {\sum\limits_{i = 0}^{n}L_{n,i}}},{where}} & (42) \\ {L_{n,i} = \left\{ \begin{matrix} {\frac{L_{w}}{2^{{\lfloor{{({i + 1})}/2}\rfloor} + 1}}\mspace{14mu}{if}\mspace{14mu} i\mspace{14mu}{is}\mspace{14mu}{even}} \\ {{\frac{L_{h}}{2^{{{({i + 1})}/2} + 1}}\mspace{14mu}{if}\mspace{14mu} i\mspace{14mu}{is}\mspace{14mu}{odd}}\mspace{31mu}} \end{matrix} \right.} & (43) \end{matrix}$ with L_(w), L_(h) the dimensions of the rectangle where the SBHT is embedded.

C. Repeater Insertion

Since trees with multiple branches typically cannot maintain a sufficiently high voltage for transmission-line propagation after two or three junctions, repeaters are needed. The criteria for repeater insertion is qualitatively similar in the rc and rlc domains. It is that of ensuring that the quadratic term in L in the time delay expression is negligible. In the regime where transmission-line effects are important (where the line in fact decouples the receiver from the driver within the time delay), it is reasonable to consider the open-ended line configuration. The criteria for selecting repeater size in the lines will be entirely different than in the rc domain. The maximum length permissible for time-of-flight computation is somewhat smaller than the optimal length of repeater insertion in the rc domain. Both of these lengths are computed with the same criteria in mind, that of ensuring that the linear term in the time domain be dominant with respect to the quadratic term. The controlling variable is: $\begin{matrix} {\psi = {\frac{rL}{2Z_{0}}.}} & (44) \end{matrix}$ Representative values for ψ might range, for instance, from 0.05 to 0.48. The size requirements for repeaters are different in both regimes. Repeater size determination in the presence of transmission lines is governed by impedance matching and the absence of overshoots and undershoots. In the absence of the latter, driver size is dictated by equation (40), which indicates smaller drivers downstream. The mechanism for repeater insertion, which is described in detail below with respect to FIG. 18, may result in repeaters being placed from source to destinations at half of the junctions.

FIG. 18 shows a flowchart of a method for minimizing reflections and placing repeaters in a SBHT. At process block 140, an optimal wire separation for a current branch is determined. The current branch may be the first branch in a SBHT clock tree (i.e., the branch coupled with the clock source) or the branch in a SBHT clock tree that is coupled directly to a repeater used to restore the signal. At process block 142, the current branch being considered is updated to the next branch in the tree. Thus, the depth of the current branch is updated so its depth i=i+1. At process block 144, a wire separation of the current branch is determined such that the impedance of the current branch matches the impedance of the previous branch. For instance, for a SBHT layout where an upstream branch is coupled in parallel with two downstream branches, the impedance Z_(i) of the current downstream branch must be twice the impedance of the adjacent upstream branch Z_(i−1). In other words, Z_(i)(s_(i))=2Z_(i−1)(s_(i−1)) 1. At process block 146, a determination is made as to whether the wire separation s_(i) calculated for the current branch is less than the maximum possible wire separation for the SBHT s_(max). The value for s_(max) may be 0.1λ, where λ is the wavelength of the electromagnetic signal propagating on the signal line. The value for s_(max) may also be found by considering other physical manufacturing restraints on the SBHT. If it is found that s_(max) is less than s_(i), then it is not possible to configure the current branch of the SBHT using the wire separation s_(i) calculated at process block 144. Thus, in process block 148, a repeater is inserted at the beginning of the branch in order to restore the signal voltage to its original value. The method for minimizing reflections is then repeated beginning with the current branch on which the repeater is placed. Because the repeater restores the signal voltage on the current branch to the signal's original value, the method may be restarted as if the current branch were the first branch in the tree. If it is found that s_(max) is less than s_(i), then the value of s_(i) calculated at process block is acceptable. At process block 150, a determination is made as to whether there are any remaining branches to be considered. In other words, a determination is made as to whether the current depth being considered (i) is less then than the total depth of the wiring layout (depth). If there are remaining branches to be considered, then at process block 152, the current branch being considered is updated to the next branch in the tree. In other words, the depth of the current branch is updated so current depth i=i+1. The impedance matching process at process block 144 is then repeated for the next branch. If it is determined that there are no remaining branches to be considered, then at process block 154, the wiring layout is complete and all branches have either matching impedances with the adjacent branches or have a repeater that restores the signal voltage to its original value.

FIG. 19 shows an exemplary wiring layout as configured by the method outlined in FIG. 18. A wiring layout 160 is shown that comprises a SBHT having a depth of five branches. A first branch 162 is denoted as having a depth of one. First branch 162 is coupled with a signal source 164, which may be an independent signal source (e.g., a clock source) or a repeater coupled with an upstream branch (not shown). First branch 162 is coupled in parallel with two other branches, including second branch 166, at a junction 168. Second branch 166 is denoted as having a depth of two. In order to minimize the reflection effects at junction 168, the impedance of the two branches are matched with the impedance of the first branch through the method outlined in FIG. 18. Thus, as is shown in FIG. 19, the wire separation s of the second branch is different than the wire separation of the first branch. A third branch 170, denoted as having a depth of three, is similarly coupled with and configured to match the impedance of second branch 166. A fourth branch 172, denoted as having a depth of four, is coupled with third branch 170. A repeater 174 is inserted at the beginning of the fourth branch to restore the signal propagated on the signal wire. In accordance with the method outlined in FIG. 18, a repeater is inserted because the wire separation s calculated to match the impedance of the third branch 170 exceeds a maximum wire separation s_(max). The method of FIG. 18 is then repeated using the fourth branch 172 as the initial branch for which an optimal wire separation is calculated using the method outlined in FIG. 4. A fifth branch 176 is coupled with and configured to match the impedance of fourth branch 172. Fifth branch 176 may then be coupled to various leaf nodes 178 that may connect with various other digital elements or combinations of elements (not shown). The leaf nodes may be connected to grids that have such a small scale that inductance effects are negligible. The delay contribution arising from the short branches in the grids can be adjusted using more traditional methods (e.g., resistance matching, buffer insertion near the destinations, etc.).

VI. Additional Considerations

The method described above for a simple sandwich configuration can be modified to account for the presence of multiple (same length) ground wires using the uniform current approximation. Specifically, in the presence of extra ground wires, the loop resistance of a signal wire connected to n ground wires in parallel becomes: r _(loop) =r _(s) +r _(GND),  (45) where rGND=(r_(g1) ⁻¹ + . . . +r _(gn) ⁻¹)⁻¹ and r_(gi) is the resistance of the ground wire i.

Similarly, the loop inductance becomes: $\begin{matrix} {{l_{loop} = {\sum\limits_{i = 0}^{n}{\alpha_{i}{\sum\limits_{j = 0}^{n}{\alpha_{j}l_{i,j}}}}}},} & (46) \end{matrix}$ with α₀=1 and $\alpha_{i} = \frac{- r_{GND}}{r_{gi}}$ for i>0.

Equations (45), (46) approach equations (6), (7), respectively, when the closer wires are those of minimum resistance (i.e., the wider ones). The replacement of equations (6), (7) with equations (45), (46) is simply an implementation detail. The c results are insensitive to the presence of non-nearest-neighbors ground wires on the same layer, due to shielding.

VII. Use of a Client-Server Network

Any of the aspects of the method described above may be performed in a distributed computer network. FIG. 20 shows an exemplary network. A server computer 180 may have an associated database 182 (internal or external to the server computer). The server computer 180 may be configured to perform any of the methods associated with the above embodiments. The server computer 180 may be coupled to a network, shown generally at 184. One or more client computers, such as those shown at 186, 188, may be coupled to the network 184 and interface with the server computer 180 using a network protocol.

FIG. 21 shows that a wiring layout may be configured according to the disclosed method using a remote server computer, such as a server computer 180 in FIG. 30. In process block 190, the client computer sends data relating to the physical parameters of the wiring layout for which an optimal wiring separation is to be calculated. In process block 192, the data is received and loaded by the server computer. In process block 194, the method disclosed above is performed and an optimal wire separation is calculated and selected. In process block 196, the client computer receives the optimal wire separation sent by the server computer.

Having illustrated and described the principles of the illustrated embodiments, it will be apparent to those skilled in the art that the embodiments can be modified in arrangement and detail without departing from such principles.

For example, the method may be used to design a wiring layout having any number of ground wires or ground surfaces surrounding a signal wire. For instance, there may be a single grounding surface surrounding the wire or there may be three or more ground surfaces surrounding the wire. Further, the method may be used to design any wiring layout for which it is desirable to have propagation at approximately the speed of light in the medium and transmission-line behavior. Moreover, if the wiring layout is a clock tree, the clock tree may have various other designs. The clock tree may have, for instance, a clock-grid design or a length-matched serpentine design.

In view of the many possible embodiments, it will be recognized that the illustrated embodiments include only examples and should not be taken as a limitation on the scope of the invention. Rather, the invention is defined by the following claims. We therefore claim as the invention all such embodiments that come within the scope of these claims. 

1. A method of configuring a wiring layout in an integrated circuit, comprising: analyzing a signal path of the wiring layout, the signal path being between a source and a destination, the signal path having multiple branches and substantially parallel ground wires spaced from and on opposing sides of at least a portion of the signal path; for an upstream branch of the signal path, determining an upstream branch layout design that produces a loop resistance, a loop inductance, and a total capacitance between the signal path and the ground wires that create a selected time delay for signal propagation along the upstream branch; and for one or more downstream branches of the signal path connected to the upstream branch, determining respective downstream branch layout designs that produce respective loop resistances, loop inductances, and total capacitances between respective signal paths and respective ground wires in the one or more downstream branches that collectively create an impedance that substantially matches an impedance of the upstream branch.
 2. The method of claim 1, wherein determining the upstream branch layout design includes changing a physical parameter of the signal path or the ground wires to produce the loop resistance, the loop inductance, and the total capacitance.
 3. The method of claim 1, wherein determining the upstream branch layout design includes calculating a wire separation between the signal path and the ground wires that produces the loop resistance, the loop inductance, and the total capacitance.
 4. The method of claim 1, wherein the substantially parallel ground wires are not equally spaced from the signal path.
 5. The method of claim 1, wherein the upstream branch layout design enables the upstream branch to exhibit transmission-line behavior.
 6. The method of claim 1, wherein the wiring layout is a clock tree.
 7. A circuit having a wiring layout configured by the method of claim
 1. 8. A computer-readable medium storing computer-executable instructions for causing a computer system to perform the method of claim
 1. 9. A client computer displaying or using a wiring layout configured by a sewer computer according to the method of claim 1, the client and server computers communicating via a network.
 10. A method of configuring a wiring layout in an integrated circuit, comprising: analyzing a signal path of the wiring layout, the signal path being between a source and a destination, the signal path having multiple branches and substantially parallel ground wires spaced from and on opposing sides of at least a portion of the signal path; and for at least one branch of the signal path, calculating an rlc relationship between the signal path and the ground wires to create a selected time delay for signal propagation along the branch, where r corresponds to a loop resistance per unit length of the signal path, l corresponds to a loop inductance per unit length of the signal path, and c corresponds to a total capacitance per unit length of the signal path, the method further including calculating a 50% time delay substantially equal to: $t_{f} + {\frac{T_{rise}}{2}{\left( \frac{V_{dd}}{V_{DM}\left( {t_{f} + \left( {T_{rise}/2} \right)} \right)} \right).}}$  where t_(f) is the time delay of a signal on the signal path, T_(rise) is the rise time of the signal on the signal path, V_(DM) is the Davis and Meindl expression for voltage of a finite open transmission line fed by a unit Heaviside pulse, and V_(dd) is the signal source voltage.
 11. A wiring layout of an integrated circuit, comprising: a signal wire for propagating a signal; and two ground wires positioned substantially parallel to and substantially equidistant from the signal wire, wherein the signal wire and ground wires are configured to create a loop resistance, a loop inductance, and a total capacitance calculated to produce a selected time delay of the signal wire, wherein the signal wire and the two ground wires form a first branch of the wiring layout, and wherein the loop resistance, the loop inductance, and the total capacitance of the first branch create a first impedance, the layout further comprising, one or more second branches of the wiring layout, each of the second branches comprising continuations of the signal and ground wires, the ground wires of the one or more second branches being positioned substantially parallel to and equidistant from the signal wire, the one or more second branches having respective loop resistances, loop inductances, and total capacitances that create a combined impedance of the second branches substantially equal to the first impedance.
 12. The layout of claim 11, wherein the loop resistance, the loop inductance, and the total capacitance are created by adjusting a wire separation between the ground wires and the signal wire.
 13. The layout of claim 11, wherein the loop resistance, the loop inductance, and the total capacitance enable the signal wire of the wiring layout to exhibit transmission-line behavior.
 14. The layout of claim 11, wherein the wiring layout is a clock tree.
 15. The layout of claim 11, wherein the loop resistance, the loop inductance, and the total capacitance are created by adjusting at least one physical parameter of the ground wires or the signal wire.
 16. A wiring layout of an integrated circuit, comprising: a signal wire for propagating a signal; and two ground wires positioned substantially parallel to and substantially equidistant from the signal wire, wherein the signal wire and ground wires are configured to create an rlc relationship that controls a time delay of the signal wire, where r corresponds to a loop resistance per unit length of the signal wire, l corresponds to a loop inductance per unit length of the signal wire, and c corresponds to a total capacitance per unit length of the signal wire, wherein the signal wire and the two ground wires form a first branch of the wiring layout, and wherein the rlc relationship is a first rlc relationship that creates a first impedance, the layout further comprising, one or more second branches of the wiring layout, each of the second branches comprising continuations of the signal and ground wires, the ground wires of the one or more second branches being positioned substantially parallel to and equidistant from the signal wire, the signal wires and ground wires in the one or more second branches being configured to create a second rlc relationship that provides a combined impedance of the second branches substantially equal to the first impedance.
 17. The layout of claim 16, wherein the first and the second rlc relationships enable the first branch and the one or more second branches of the wiring layout to exhibit transmission-line behavior.
 18. The layout of claim 16, wherein the first and the second rlc relationships enable the first branch and the one or more second branches of the wiring layout to propagate a signal at or near the speed of light in the signal wire.
 19. The layout of claim 16, wherein the wiring layout is a clock tree. 